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ACM Transactions on Computer Systems (TOCS), Volume 35 Issue 3, December 2017

Seer: Probabilistic Scheduling for Hardware Transactional Memory
Nuno Diegues, Paolo Romano, Stoyan Garbatov
Article No.: 7
DOI: 10.1145/3132036

The ubiquity of multicore processors has led programmers to write parallel and concurrent applications to take advantage of the underlying hardware and speed up their executions. In this context, Transactional Memory (TM) has emerged as a simple...

The Hipster Approach for Improving Cloud System Efficiency
Rajiv Nishtala, Paul Carpenter, Vinicius Petrucci, Xavier Martorell
Article No.: 8
DOI: 10.1145/3144168

In 2013, U.S. data centers accounted for 2.2% of the country’s total electricity consumption, a figure that is projected to increase rapidly over the next decade. Many important data center workloads in cloud computing are interactive, and...

Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors
Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
Article No.: 9
DOI: 10.1145/3148052

Corrigendum to “The IX Operating System: Combining Low Latency, High Throughput and Efficiency in a Protected Dataplane”
Adam Belay, George Prekas, Mia Primorac, Ana Klimovic, Samuel Grossman, Christos Kozyrakis, Edouard Bugnion
Article No.: 10
DOI: 10.1145/3154292