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Leveraging Core Specialization via OS Scheduling to Improve Performance on Asymmetric Multicore Systems
Juan Carlos Saez, Alexandra Fedorova, David Koufaty, Manuel Prieto
Article No.: 6
Asymmetric multicore processors (AMPs) consist of cores with the same ISA (instruction-set architecture), but different microarchitectural features, speed, and power consumption. Because cores with more complex features and higher speed typically...
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
Article No.: 7
Cores in chip-multiprocessors (CMPs) share multiple memory subsystem resources. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed separate fairness...
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron
Article No.: 8
Modern graphics processing units (GPUs) employ a large number of hardware threads to hide both function unit and memory access latency. Extreme multithreading requires a complex thread scheduler as well as a large register file, which is expensive...