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ACM Transactions on Computer Systems (TOCS), Volume 25 Issue 1, February 2007

Specifying memory consistency of write buffer multiprocessors
Lisa Higham, Lillanne Jackson, Jalal Kawash
Article No.: 1
DOI: 10.1145/1189736.1189737
Write buffering is one of many successful mechanisms that improves the performance and scalability of multiprocessors. However, it leads to more complex memory system behavior, which cannot be described using intuitive consistency models, such as...

Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates
Ilya Gluhovsky, David Vengerov, Brian O'Krafka
Article No.: 2
DOI: 10.1145/1189736.1189738
Cache miss rates are an important subset of system model inputs. Cache miss rate models are used for broad design space exploration in which many cache configurations cannot be simulated directly due to limitations of trace collection setups or...

Trace cache sampling filter
Michael Behar, Avi Mendelson, Avinoam Kolodny
Article No.: 3
DOI: 10.1145/1189736.1189739
A simple mechanism to increase the utilization of a small trace cache, and simultaneously reduce its power consumption, is presented in this article. The mechanism uses selective storage of traces (filtering) that is based on a new concept in...